This invention relates to a semiconductor device, and in particular to a power semiconductor device such as an accumulation layer emitted thyristor (ALET) and to a large class of high to ultra-high voltage devices such as diodes, DMOSFETs, DMOS IGBTs, trench MOSFETs and trench IGBTs.
In order to prevent voltage breakdown at the edges of a power semiconductor device such as an ALET, the device (which is typically built in a relatively large silicon wafer) is provided with a termination structure. A standard termination structure utilises a floating ring termination technique having, say, p-type regions (rings) in a surface layer surrounding the active region (of n-type material) of the device.
The success of a controllable semiconductor device at high or ultra-high voltages is almost entirely determined by a successful implementation of the edge termination. There are three main reasons which make the termination problem more difficult as the voltage ratings increase. Firstly, the number of floating rings increases significantly, and thus the wasted area and the ratio between the wasted area and the active area increases. This results in a poorer yield and a higher on-state voltage. Secondly, as the voltage increases, and accordingly the doping concentration of the base decreases, the device is more prone to parasitic field charge or passivation charge effects, which may cause premature breakdown. Thirdly, as the number of rings increases, the control of the depth and spacing between the rings becomes even tighter than that for a relatively-lower voltage termination, and therefore the termination effectiveness is very susceptible to process variations.
The present invention provides a semiconductor device comprising an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device, the edge portion comprising a substrate region of a first semiconductor type, wherein the voltage termination structure comprises first and second layers formed within the substrate region, the first and second layers defining regions each of a second semiconductor type.
Preferably, the first and second layers of the voltage termination structure each comprises a plurality of semiconductor regions.
In a preferred embodiment, the edge portion surrounds the active area, the first and second layers of the voltage termination structure extending around the edge portion. Conveniently, the first and second layers of the voltage termination structure are formed as rings.
Advantageously, the first layer of the voltage termination structure is formed in the region of an upper surface of the substrate region, the second voltage termination layer being formed beneath the first layer. Preferably, a cathode is formed on the first layer on said upper surface of the substrate region, and an anode is formed on an opposite surface of the substrate region. In the off-state of the device, the voltage potential, against which the termination structure provides edge breakdown protection, is coupled between the cathode and the anode.
Preferably, the first substrate region is formed of n-type semiconductor material, and the first and second layers of the voltage termination are formed of p-type semiconductor material, and the substrate region comprises first and second substrate layers. In the latter case, the second voltage termination layer is located at the junction between the first and second substrate layers, the first substrate layer is an epitaxial layer, and the second substrate layer is a drift layer.
Advantageously, the active area comprises a gate portion in the form of a trench which extends from an upper edge of the substrate region into an active area substrate region.
Conveniently, the plurality of semiconductor regions comprising the second voltage termination layer are formed so as to be equidistant to each other.
Preferably, the plurality of semiconductor regions comprising the second voltage termination layer are formed so as to provide an optimised potential distribution.
The semiconductor regions may be formed as separate rings, or as a mesh arrangement. It will be appreciated that the separate rings are not necessarily circular, but should substantially surround the active area of the device.
In a preferred embodiment, the plurality of semiconductor regions comprising the first voltage termination layer are formed so that their upper edges are in alignment with an upper edge of the active area of the device.
Advantageously, the semiconductor regions comprising the first voltage termination layer are arranged adjacent to one another. Preferably, the doping concentration of the semiconductor regions comprising the first voltage termination layer decreases as the distance from the active area of the device increases.
In a preferred embodiment, the semiconductor regions of the first voltage termination layer are floating p+ rings in the upper part of the substrate region.